Efficient Approximate 4-2 Compressors and Error Compensation Strategies for Approximate Multipliers

Approximate computing is widely used to trade off computation precision for improved performance and energy efficiency. As multiplier is one of the most frequently used arithmetic units in digital systems, the design of approximate multiplier has gained much attention. Among all approximate multiplication techniques, designing approximate compressor for partial product accumulation is one of the popular choices. However, current designs do not comprehensively analyze error characteristics so that there is still a large space to improve the resource efficiency for compressors. In this paper, two (4, 2)-approximate compressor architectures are proposed for energy efficient approximate multipliers. The first design only contains two OR gates which significantly improves the resource consumption of the multiplier but the approximation error is relatively large. To reduce its approximation error, the second compressor is proposed by adding error correction circuits to the first design. However, this may lead to an increase in the area of the multiplier. To keep the multiplier area to be small, an efficient error compensation strategy is proposed by analyzing the error characteristics in the scope of the whole multiplier array. Finally, by using the proposed compressors, efficient approximate multiplier architectures are proposed. Implementation results show that the proposed design can achieve much better hardware metrics while maintaining low approximation errors when compared with previous designs. The proposed designs are also applied in image sharpening application to verify their effectiveness.